1. Field of the Invention
The present invention relates to a clock generation circuit for generating a clock having a multi-level frequency suitable to a frequency demanded by a system or an apparatus, etc. operating in synchronization with a clock, and a clock conversion circuit.
2. Description of the Related Art
Power consumption in a system or an electronic apparatus having installed therein an electronic circuit is proportional to a frequency of a clock for driving the system or the apparatus. In many systems or electronic apparatuses of the related art installed with an electronic circuit, however, a frequency of a clock to be supplied is determined in accordance with a task to be processed at the highest speed among required tasks and a clock having this frequency is always supplied. Accordingly, even when the processing of a required task is light, it is driven with a high frequency clock, and thus, there is a disadvantage that the power consumption is always large regardless of the tasks.
To deal with this disadvantage, there has been a technique of preparing a plurality of clocks in advance and switching the clock in accordance with the processing speed of each task when there are tasks requiring heavy processing and when there are tasks requiring light processing, particularly in a portable electronic apparatus, etc., which require a reduction of excessive power consumption.
In this technique, however, only the previously prepared kinds of frequency clocks can be supplied. A required minimum frequency differs in a variety of tasks, so the current frequency switching technique does not completely suit the required minimum frequencies of the variety of tasks. For example, when switching a frequency between 50 MHz and 100 MHz, a clock of 50 MHz is sufficient for tasks operating at 50 MHz at a minimum, but when a task operating at a clock of, for example, 80 MHz at a minimum interrupts, the operating frequency of the whole system or apparatus is switched to 100 MHz. Consequently, the clock becomes excessively higher by 20 MHz than what is required and power is wasted by that amount in terms of power consumption.
To prevent this disadvantage, a supply of frequencies having more gradual multi-levels has to be realized in order to cover the minimum operation frequencies of all assumed tasks. However, it is impossible to cover the minimum operation frequencies of all tasks in a system or electronic apparatus wherein circuits operate in a complicated manner. Even when it is realized, a load on a clock generation circuit becomes heavy because of the requirement that many kinds of frequency clocks be prepared in advance.
Accordingly, the clock frequencies are switched by rough divisions, such as at the time of driving with batteries or an AC power source, or at the time a high-speed clock is required, and excessive power consumption due to the incongruity of frequencies is permitted to a certain extent in many cases.
An object of the present invention is to provide a clock generation circuit including a configuration wherein excessive power consumption is reduced as much as possible while using a clock generated at a certain cycle, and a clock conversion circuit.
According to a first aspect of the present invention, there is provided a clock generation circuit, comprising a clock generation unit for generating a clock with a constant frequency; a counter operating in synchronization with the clock for counting pulses of the clock; a comparator for comparing a counter value of the counter with the number of pulses of a clock having a desired frequency; and an output gate for controlling the supply and stopping of pulses of the clock input from the clock generation unit based on a comparison result of the comparator.
The clock conversion circuit according to the first aspect of the present invention comprises a counter operating in synchronization with an input clock for counting pulses of the clock; a comparator for comparing a counter value of the counter with the number of pulses of a clock having a desired frequency; and an output gate for controlling the supply and stopping of pulses of the input clock based on a comparison result of the comparator.
In the first aspect, when the clock generation unit generates a clock with a constant frequency or a clock with the constant frequency is input from the outside, the clock is supplied to the counter and the output gate. The counter counts pulses thereof in synchronization with the clock. The comparator monitors a counter value of the counter and compares the value with the number of pulses of a clock having a desired frequency. The output gate controls the supply and stopping of pulses of the input clock. Since the control is performed based on a comparison result of the comparator, the input clock is adjusted to have the number of pulses equivalent to a desired frequency per same unit of time and output from the output gate.
According to a second aspect of the present invention, there is provided a clock generation circuit, comprising a clock generation unit for generating a clock with a constant frequency; a counter operating in synchronization with the clock for counting pulses of the clock; a conversion circuit for performing data conversion on the counter value of the counter and outputting the same; a comparator for comparing an output value of the conversion circuit with the number of pulses of a clock having a desired frequency; and an output gate for controlling the supply and stopping of pulses of the clock input from the clock generation unit based on a comparison result of the comparator.
A clock conversion circuit according to the second aspect of the present invention comprises a counter operating in synchronization with an input clock for counting pulses of the clock; a conversion circuit for performing data conversion on a counter value of the counter and outputting the same; a comparator for comparing an output value of the conversion circuit with the number of pulses of a clock having a desired frequency; and an output gate for controlling the supply and stopping of pulses of the input clock based on a comparison result of the comparator.
In the second aspect, a counter, comparator and output gate having the same functions as those in the first aspect are provided and a conversion circuit is furthermore provided. The conversion circuit performs data conversion of, for example, replacing an arrangement of pulses on a counter value of the counter and outputs the same. The comparator in this case compares an output value of the conversion circuit with the number of pulses of a desired frequency. The output gate for supplying and stopping the pulses based on the comparison result of the comparator outputs, while it depends on the data conversion performed by the conversion circuit, a clock wherein pulse stopping positions are more dispersed than in the case of the first aspect in accordance with conversion when the conversion is, for example, to replace bits.
According to a third aspect of the present invention, there is provided a clock generation circuit, comprising a clock generation unit for generating a clock of a frequency; a first counter for counting in synchronization with the clock; a second counter for counting in synchronization with the clock every time the first counter overflows; a comparator for comparing the counter value of the second counter with a value corresponding to a frequency difference between a frequency of the clock and a desired frequency; and an output gate for controlling the supply and stopping of pulses of the clock based on a comparison result of the comparator and outputting a clock wherein the frequency difference is corrected.
A clock conversion circuit according to the third aspect of the present invention comprises a first counter for counting in synchronization with an input clock; a second counter for counting in synchronization with the clock every time the first counter overflows; a comparator for comparing a counter value of the second counter with a value corresponding to a frequency difference between a frequency of the clock and a desired frequency; and an output gate for controlling the supply and stopping of pulses of the clock based on a comparison result of the comparator and outputting a clock wherein the frequency difference is corrected.
In the third aspect, a plurality of counters, two in this case, for operating to count in synchronization with the input clock are provided. The second counter of the two operates to count every time the first counter overflows. The comparator compares the counter value of the second counter with a value corresponding to a frequency difference between a frequency of the clock and a desired frequency every time the first counter overflows. The output gate controls the supply or stopping of pulses of the clock based on the comparison result of the comparator, so a clock wherein the above frequency difference is corrected is output from the output gate.
According to a fourth aspect of the present invention, there is provided a clock generation circuit, comprising a clock generation unit for generating a clock with a constant frequency; a first counter for counting in synchronization with the clock; a second counter for counting in synchronization with the clock every time the first counter overflows; a conversion circuit for performing data conversion on a counter value of the second counter and outputting the same; a comparator for comparing an output value of the conversion circuit with a value corresponding to a frequency difference between a frequency of the clock and a desired frequency every time the first counter overflows; and an output gate for controlling the supply and stopping of pulses of the clock based on comparison results of the comparator and outputting a clock wherein the frequency difference is corrected.
A conversion circuit according to the fourth aspect of the present invention comprises a first counter for counting in synchronization with an input clock; a second counter for counting in synchronization with the clock every time the first counter overflows; a conversion circuit for performing data conversion on the counter value of the second counter and outputting the same; a comparator for comparing an output value of the conversion circuit with a value corresponding to a frequency difference between a frequency of the clock and a desired frequency; and an output gate for controlling the supply and stopping of pulses of the clock based on a comparison result of the comparator and outputting a clock wherein the frequency difference is corrected.
In the fourth aspect, a conversion circuit in the second aspect is furthermore added to the configuration of the third aspect. The comparator in this case compares an output value of the conversion circuit with a value corresponding to a frequency difference between a frequency of a clock with a desired frequency. When a conversion format of the conversion circuit and the number of bits to be repeatedly counted by the counter are suitably selected, the output gate for outputting the supply and for stopping pulses in accordance with the comparison result outputs a clock having a desired frequency wherein pulse stopping positions are uniformly dispersed as a whole.